Semiconductor chips are used in many applications, including as integrated circuits and as flash memory for computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices. Moreover, it is desirable that the devices operate at very fast speeds.
Among the things that can limit the speed with which semiconductor devices operate is extraneous capacitances in the devices. More specifically, undesired electrical capacitance can arise from the portions of the source and drain regions that overlap the gate region, as well as from the source and drain junctions. To limit junction depth and, hence, to decrease junction capacitance, so-called “silicon on insulator” (“SOI”) technology, can be used in which a layer of oxide is buried in the silicon substrate to act as a stop to dopant diffusion (and, hence, to act as a stop to source/drain junction depth).
On top of this layer of oxide may reside a silicon region, commonly referred to as the “body.” In the body, active regions, e.g., source and/or drain junctions, and shallow trench isolation (STI) regions may be formed. On top of the body, a polysilicon gate may be separated from the body by a layer of gate oxide. However, if the gate oxide breaks down, a conductive path is formed between the gate and the channel or body. This may result in shifts in the threshold voltage from charge trapping thereby resulting in the defective operation of the SOI device.
One method for detecting defects, such as a gate oxide breakdown, is passive voltage contrast. In the passive voltage contrast technique, a scanning electron microscope (SEM) may direct electrons to an integrated circuit or wafer placed on a stage in a vacuum chamber. Upon directing electrons onto the test circuit or wafer, secondary electrons may be produced. These secondary electrons may be produced by interconnected structures. That is, secondary electrons may be produced when there is a conductive path for electrons to flow. The areas of a conductive path may be brighter than the areas in which there is not a conductive path based on the amount of secondary electrons produced. By determining if the area around the gate oxide region is dark or bright, a determination may be made as to whether there is a breakdown in the gate oxide region. If there is a breakdown in the gate oxide region, then the area will appear to be bright. The area will appear bright since a conductive path has been formed from the gate to the channel thereby resulting in secondary electrons being produced. If there is not a breakdown in the gate oxide region, then the area will appear dark.
However, the passive voltage contrast technique has not been able to be applied to detect breakdowns in the gate oxide regions in SOI semiconductor devices because SOI devices have included an insulator between the body and the substrate. This insulator prevents a conductive path forming from the gate to the substrate even when there is a breakdown in the gate oxide. Hence, the passive voltage contrast technique may indicate a dark area even when there is a breakdown in the gate oxide. Consequently, the passive voltage contrast technique cannot currently be performed on SOI semiconductor devices to detect a breakdown in the gate oxide. Similarly, the passive voltage contrast technique cannot currently be preformed on SOI semiconductor devices to detect an open contact since closed contacts would appear to be open as the insulator in the SOI semiconductor device prevents a conductive path forming from the contact to the substrate.
Therefore, there is a need in the art to be able to perform passive voltage contrast on an SOI semiconductor device to detect a breakdown in the gate oxide as well as to detect open contacts.